1. Technical Field
The present disclosure relates to memory systems. More particularly, the present disclosure relates to a memory system protected from errors caused by read disturbances and a method thereof.
2. Discussion of Related Art
Technologies for detecting and correcting errors provide effective recovery of data that are damaged due to various reasons. For example, while storing data in a memory, the data may be damaged by perturbations in transmission channels through which the data are transferred from a source location to a target location.
Conventional technologies for error detection and correction include the use of Reed-Solomon (RS) codes, Hamming codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and cyclic redundancy codes (CRC). These codes can be used to detect and correct damaged or faulty data.
Data may be stored in nonvolatile memories (e.g., flash memories) together with coded values called error correction codes (hereinafter, referred to as ‘ECC data’). The ECC data may be used to correct errors generated during a read-out operation of the flash memory. However, there is a limit to the number of bits that may be corrected using the ECC data. FIG. 1 is a circuit diagram of a conventional flash memory device and FIG. 2 is a timing diagram showing a read-out operation of the flash memory device of FIG. 1.
The flash memory includes a memory cell array having a plurality of memory blocks. FIG. 1 shows a unit memory block BLK. The memory block BLK is formed of NAND strings, each coupled to a different bit line. Each string includes a string selection transistor SST, a ground selection transistor GST, and memory cells (e.g., cell transistors) MC0˜MCn−1 connected between the selection transistors SST and GST in series. The gates of the selection transistors SST and GST are connected to a corresponding NAND string and ground selection lines SSL and GSL, respectively. The control gates of the cell transistors MC0˜MCn−1 are coupled each to their corresponding word lines WL0˜WLn−1. Bit lines BL0 and BL1 are connected to their corresponding page buffers PB.
During a read-out operation, as shown in FIG. 2, a selected word line (e.g., WL0) is driven to a voltage of 0V while deselected word lines (e.g., WL1˜WLn−1) are driven to a read voltage Vread. Accordingly, the string and ground selection lines SSL and GSL are driven to the read voltage Vread. The page buffers PB supply the bit lines BL0 and BL1 with sensing currents.
The voltages of the bit lines BL0 and BL1 are determined by the states of the memory cells that are coupled to a selected word line. For example, when a memory cell coupled to a selected word line is an on-cell, a voltage of its corresponding bit line decreases to a ground voltage. Alternately, when a memory cell coupled to a selected word line is an off-cell, a voltage of its corresponding bit line increases to a power voltage. The voltage of the bit lines are sensed by their corresponding page buffers PB as cell data.
For convenience of description, a memory cell coupled to a deselected word line is hereinafter referred to as ‘deselected memory cell’ and a memory cell coupled to a selected word line is hereinafter referred to as ‘selected memory cell’.
When cell data is read from selected memory cells, the read voltage Vread is applied to word lines of deselected memory cells. The read voltage Vread is set to a level that is large enough to turn on cell transistors that are set to an off state.
During the read-out operation, the read voltage Vread is applied to control gates of the deselected cell transistors and the ground voltage is applied to a substrate (e.g., a bulk) of the deselected cell transistors. The drains of the deselected cell transistors are supplied with a predetermined voltage. The application of the read voltage Vread and the ground voltage causes a bias condition during the read-out operation.
As illustrated in FIG. 3, the bias condition can cause electrons to be injected into a floating gate of the deselected cell transistor from the substrate during the read-out operation. The electrons can result in an unintentional programming (or soft programming) of a deselected cell transistor in on-state (or erased state), which is referred to as a ‘read disturbance’.
A read disturbance may cause threshold voltages of the on-state (or erased state) memory cells to gradually increase. As noted by the shaded area shown in FIG. 4, threshold voltages of the on-state memory cells increase in proportion to number of read-out operations that are performed. The voltage increases may cause some of the on-state memory cells to be erroneously detected as off-cells, resulting in read fails.
As the number of read-out operations performed increases, the probability of a read fail increases as shown in FIG. 5. If the number of bit errors exceeds a permissible range, a block corresponding thereto is treated as a bad block. The bad block containing the erroneous data is replaced by a reserved memory block, which is stored in the flash memory device. Here, the bad block is caused by a read disturbance, and not worn out by repetition of the programming or reading operation. Therefore, the bad block may be reused through erasure and replacement.
However, repeated reading of several pages of the block, may damage data of other pages. For example, when repeatedly reading a music file, which is stored in a specific page using an MP3 player, a read disturbance may occur because the read voltage Vread is continuously applied to the other pages of the block. However, error correction cannot be performed when there are too many bit errors.
Thus, there is a need for memory systems and methods thereof that can protect memories from bit errors caused by read disturbances.